Full Chip Layout Design

This comprehensive course is designed to equip engineers with the skills necessary for Full Chip layout. Full Chip Layout refers to the process of translating Full Chip Schematic into Physical Design. It involves consolidation of blocks (analog and digital), P&R blocks, Power Transistors, Memory Cells and other devices depending on the purpose of the Chip being created. It is at this stage that positions of PAD’s were set so that it can be properly connected to the desired chip packaging. Through a combination of lectures, actual demonstration, practical exercises and hands-on chip exercise, participants will develop the skills necessary to create a quality Full Chip layout.

By the end of this course, participants will be able to:

• Learn about important flows in Physical Design
  
  • Major Step in IC design Flow
  • Physical Design Flow
• Understand Full Chip Parts and Its Functions
  
  • Die Area/Chip Size
  • Accessories
  • PAD’s
  • Input/Output Cells
  • Core Circuit
    
    • Power Transistors
    • Laser Trimmings (Fuse)
• Learn the different placement hierarchical approach
  
  • Top-Down Approach
  • Bottom-Up Approach

• Module 1: Full Chip Introduction
• Module 2: Full Chip Floorplanning (Top-Down Approach)
• Module 3: Full Chip Floorplanning (Bottom-Up Approach)

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