Full Chip Layout: Floor planning and Routing

This comprehensive course is designed to equip engineers with the skills necessary for Full Chip layout. Full Chip Layout refers to the process of translating Full Chip Schematic into Physical Design. It involves consolidation of blocks (analog and digital), P&R blocks, Power Transistors, Memory Cells and other devices depending on the purpose of the Chip being created. It is at this stage that positions of PAD’s were set so that it can be properly connected to the desired chip packaging. Through a combination of lectures, actual demonstration, practical exercises and hands-on chip exercise, participants will develop the skills necessary to create a quality Full Chip layout.

By the end of this course, participants will be able to:

• Perform Full Chip Floorplanning
  
  • Be able to create a Floorplan that will utilize target Die Area/Chip Size while achieving its desired function.
  • Learn proper estimation (placement and routing)
  • Knowing floorplan considerations necessary in overcoming common challenges in floorplan creation.
• Implement Full Chip routing, verification and quality checking
• Engage in hands-on exercises to reinforce theoretical knowledge

• Module 4: Full Chip Routing
• Module 5: Full Chip Verification
• Module 6: Full Chip Quality Checking

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