Techniques and Methodologies in Standard Cell Layout

This comprehensive course is designed to equip engineers with the skills and knowledge in Standard Cell Development and as a continuing course after Introduction to Standard Cell Layout course. This course thoroughly introduces digital design, focusing on CMOS logic circuits, layout techniques, and verification processes for simple cells. Participants will gain hands-on experience in planar technology, and various layout and verification exercises in working with simple cells.This foundational course provides a comprehensive introduction to Standard Cell Development. Participants will explore the fundamentals of semiconductors and gain practical familiarity with the Unix environment, the standard operating system used in IC design workflows. The course covers planar technology concepts, focusing on the methodologies used in creating standard cells from the ground up.  Learners will progress from basic stick diagrams to simple cell layouts, emphasizing from-scratch layout implementation and usage of EDA tools.

By the end of this course, participants will be able to:

• Understand the fundamentals of standard cell implementation
• Create and interpret stick diagrams
• Operate design tools
• Create and verify simple cell layouts
• Perform physical verifications

• Module 1: Refresher to Standard Cell (Planar)
• Module 5: Node Familiarization
• Module 6: Physical Verification
• Module 7: Hands-on: Simple Cells

• Layout Tool: Google Skywater
• Verification Tools: Google Skywater